1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, a pattern detection method and a serial-parallel conversion method suitable for serial-parallel conversion in a high-speed interface circuit.
2. Description of the Related Art
In recent years, Serializer/Deserializers (SerDes) have been adopted as a high-speed serial interface for buses or the like of computers. A deserializer used in a SerDes has a circuit portion configured to convert serial data into parallel data and a circuit portion configured to detect a sync pattern in the converted parallel data and convert the parallel data into a desired form.
That is, in the deserializer, received serial data is successively transferred to and stored in a plurality of shift registers by using a high-speed clock signal. After a predetermined number of bits of the data have been stored in the shift registers, the data is transferred in parallel form from the shift registers by using a low-speed clock signal.
Subsequently, for synchronization, this parallel data is transferred to a circuit called a framer. The framer has a plurality of shift registers on a predetermined bit-by-bit basis, a plurality of sync pattern detection circuits and selecting circuits. From a plurality of parallel data items stored in the plurality of shift registers, a sync pattern is detected by the sync pattern detection circuits and a frame according to the position at which the sync pattern is detected is selected by the selecting circuits. In this way, parallel data synchronized with the sync pattern can be obtained from the selecting circuits. This system enables reception of transmitted data with reliability.
A serial/parallel conversion circuit of this kind is described in detail in Japanese Patent Application Laid-Open Publication No. 11-145944.
However, the framer operates by a low-speed clock signal and therefore has the drawback of increasing the latency and decreasing the performance. It is possible to reduce the latency by reducing the number of shift register stages in the framer. However, doing so necessitates drive of a comparatively large number of sync pattern detection circuits and selecting circuits and causes an increase in fan-out, resulting in a reduction in communication speed of the deserializer. Conversely, decreasing the fan-out in order to improve the communication speed of the deserializer causes an increase in latency, resulting in a considerable decrease in performance and increase in circuit area. Further, the framer requires a plurality of sync pattern detectors and selecting circuits and needs a comparatively large circuit area.